This invention relates to non-volatile memory sharing, in particular, a flash memory, EEPROM device, or battery backup memory sharing system for multiple processors and a related method thereof.
In order to maintain cost effectiveness for new and rapidly growing technologies, electronics manufacturers continually search for methods and architectures to reduce design constraints, component usage and overall resource requirements. This line of forward thinking helps ensure that electronic devices remain affordable and effective as various technologies continue to improve and expand over time.
One particular area that experiences rapid growth is networking, or more specifically, memory sharing through a network of computer processing units (processors). This not only includes local area and macroscopic networks, but also IC's and portable devices which utilize multiple processors or processors in joint operation. In order to reduce component costs for multiple processors circuits, and to enhance data sharing and local networking functionalities, some device and network configurations utilize shared flash memory architectures. Not only does sharing a single flash memory help reduce component costs, it reduces vital PCB area on circuit boards and allows otherwise consumed PCB area to be devoted for other circuitries. One key advantage of utilizing flash memory is that it is non-volatile, meaning that it does not need power to maintain the information stored in the chip. This is the main reason why many flash memory units are used to store instruction set program codes for processors to execute upon startup. In addition, flash memory offers fast read access times (although not as fast as volatile DRAM memory used for main memory in PCs) and better shock resistance than traditional hard disks. These characteristics help explain the popularity of flash memory for applications such as storage on battery-powered devices.
FIG. 1 illustrates a traditional flash memory sharing apparatus 100 between multiple processors according to the related art. The apparatus 100 includes a plurality of processors 110, a bus arbitrator 120 coupled to the plurality of processors 110, and a flash memory unit 130 coupled to the bus arbitrator 120. When one of the processors of the plurality of processors 110 wishes to access data in the flash memory 130, it must provide a read or write request to the bus arbitrator 120. The processor may be trying to access its instruction set stored in the flash memory 130, or it may be simply trying to access general data. The bus arbitrator acts as a router of sorts, and simply separates the time usage of the flash memory 130 between the plurality of processors 110. This provides a direct access connection between the flash memory 130 and the processor initiating the access request. For example, If only one processor of the plurality of processors 110 requests access the flash memory 130, it will temporarily possess sole exclusive access to it. However, if another processor also requests access, the bus arbitrator 120 will then split access between the requesting processors and flash memory 130 by dividing the time allocated to each processor for communicating with the flash memory. Allocation of the access time to the flash memory 130 by the bus arbitrator 120 is therefore a function of the number of processor that request access to the flash memory 130 and their relative priority of access (if applicable).
Although the flash memory sharing apparatus 100 may provide acceptable performance characteristics for networks with limited numbers of processors, some problems may develop when the number of processors 110 in the network increases. When more processors 110 are introduced into the apparatus 100, the bandwidth allocated to each processor 110 becomes reduced, thereby slowing down performance and access time durations to the flash memory 130. This is because the bus arbitrator 120 is now forced to share access to the flash memory 130 with the additional processors 110, further limiting the time allotted to each processor 110 to access to the flash memory 130. For high performance processor 110 applications, such as realtime DSP, this may result in unacceptably slow seek and access times, and possibly even system failure.
Furthermore, this apparatus 100 requires the use of a bus arbitrator 120, which adds to the component and design costs to the apparatus 100, and consumes valuable PCB space if designed onto a circuit board. Also, because the bus arbitrator 120 simply provides direct access (or a direct connection) to the flash memory 130, the requesting processor will have complete access to the flash memory 130 regardless of security permissions or concerns.